High Level Static Analysis of System Descriptions for Taming Verification Complexity

High Level Static Analysis of System Descriptions for Taming Verification Complexity

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Antecedent conditioned slicing, an abstraction technique for reducing RTL design space is introduced. The reduced RTL can then be model checked. An open source RTL implementation of the USB 2.0 protocol is verified using this technique.Our tool is effective in verifying multiplier designs that are modifications (usually for optimization)to standard multipliers like Booth, Wallace Tree and Array multipliers. We used the tool for verifying the Verilog implementation of BISMUL [ 249], anbsp;...


Title:High Level Static Analysis of System Descriptions for Taming Verification Complexity
Author: Shobha Vasudevan
Publisher:ProQuest - 2007
ISBN-13:

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